Lower and more aggressive gate pitch scaling, for example, beyond the 14 nm node, calls for sidewall imaging transfer (SIT) to form gates because a sub-80 nm pitch typically cannot be formed reliably by a single path of conventional lithography.
Conventional SIT processes, where only one critical dimension can be achieved, result in all gates having the same length, which contradicts multiple length (multiple-L) gate requirements in various complementary metal oxide semiconductor (CMOS) devices. Having different gate lengths in CMOS devices can be an important feature with various applications, such as achieving multiple threshold voltages.
Using multiple SIT paths to form multiple-L gates adds processing cost and complexity, as it is not trivial to perform patterning with thin and high aspect ratio SIT spacers. Therefore, there is a need for an improved process for forming multiple-L gates.